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This thesis studies the development of a prototype reconfigurable 32 channel digitizer ASIC for intracardiac echocardiography (ICE) catheters. The aim is to develop a chip containing the core components (Analog front-end, ADC and power supply regulation), designed and combined in such a way that the overall system is power- and area-efficient, such that the limiting factors to such a system can be identified. Chapter 1 introduces the background behind this thesis, examines research trends and introduces the overall system. It examines design trade-offs related to splitting an ultrasound imaging catheter into two ASICs: a front-end ASIC in a larger, high-voltage technology to allow for high-voltage pulsers; and a low-voltage back-end ASIC in 40nm CMOS containing the digitizer and digital circuitry to improve digital efficiency. The chapter concludes with an overview of target specifications and a summary of the contents of the thesis. In Chapter 2, a compact, multipurpose analog front-end (AFE) is developed. It uses a separate capacitive feedback amplifier and filter stage to reduce the area of passive components and the power needed to drive them. The core amplifiers use a self-biased inverter-based amplifier for its power efficiency, and class AB operation to efficiently drive the peak loads during ADC input sampling. The power-efficiency and chip area of this AFE are in line with state of the art stand-alone filters, while extra functionality like AC coupling, single-ended to differential conversion, gain and ADC input driving allow for more efficient integration into a larger system. Chapter 3 shows design trade-offs for ADCs and their impact on surrounding blocks in a larger system. It argues the use of SAR ADCs with a charge-redistribution DAC using a delta-length capacitor layout for power-efficiency and linearity, and shows the implementation of such an ADC. This ADC does not exceed the state of the art in any single metric, but it is one of the best performing published designs when considering both power efficiency (Schreier FOM) and area. In Chapter 4, the use of LDOs in the context of a catheter digitizer is analyzed. Segmentation of loads into different supply domains is shown, and the design and stand-alone performance of 3 buffered flipped voltage follower (FVF) LDOs is presented. While the performance of this common type of LDO is not exceeding the state-of-the-art, instead the designs in this chapter focusses on LDOs suitable for the actual ICE catheter application. The integration of the ASIC is shown and analyzed in Chapter 5, establishing that the power consumption is balanced between different blocks, AFE linearity is limiting overall system linearity, and the majority of chip area is used by on-chip decoupling. Staggering conversion clocks in time to spread load current and to reduce supply regulation requirements is shown, along with dynamic control of AFE settings to adapt to the changing operating conditions during a receive cycle. Compared to other work, the combination of small area and low power make this digitizer exceptionally suited for integration in ultrasound imaging catheters. Chapter 6 shows passive-switched capacitor circuits as an alternative to perform single-ended to differential conversion in low to medium resolution converters. While this concept was not used in the main chip, this approach has an inherent scaling of power with ADC sampling frequency and overall low power and area. The input sampling period can also be longer than that of a typical SAR ADC. Chapter 7 examines potential changes to on-chip power supplies in the main chip to reduce the area of decoupling capacitance by changing the amount of decoupling, using higher density capacitors and using active/switched methods to enhance decoupling capacitance. Finally, Chapter 8 concludes the thesis, highlights the limitations of the current implementation and discusses potential future work related to this.