IAIONEX SYSTOLIC_GEMM_CORE_V2 — Deterministic Systolic Matrix Multiplication Accelerator for Reproducible Hardware Compute Experiments

ZENODO_DESCRIPTIONIAIONEX SYSTOLIC_GEMM_CORE_V2 is a deterministic systolic array compute accelerator implementingmatrix multiplication (GEMM) hardware for reproducible compute experiments. The accelerator implements a hardware systolic pipeline architecture designed fordeterministic evaluation of matrix multiplication workloads and integration intoreproducible compute pipelines. The architecture is designed to operate within offline deterministic build environmentswhere artifacts, build outputs and verification data are bound to cryptographic manifests. The release archive contains the complete hardware design and verification bundle: • RTL hardware implementation of the systolic GEMM core • Simulation testbench used for functional verification • synthesis and build scripts used during hardware evaluation • verification artifacts generated during the build process • SHA-256 integrity manifests for all artifacts The artifacts included in the package are generated in a deterministic offline executionenvironment and are bound to SHA-256 verification manifests to support reproduciblebuild validation. System identifier used in artifacts: SYS_UID = IAIONEX.70ID The release is part of the IAIONEX deterministic computing platform which focuses onreproducible compute pipelines, deterministic execution environments and hardwareaccelerated compute architectures. The IAIONEX platform operates with offline reproducible build workflows wherehardware artifacts, verification outputs and manifests are bound to deterministicexecution environments. Author Johan Gärtner IAIONEX.AB ORCID: 0009-0001-9029-1379