An efficient excess-6 select BCD adder in 90 nm technology for fast decimal arithmetic units

Abstract This paper presents a new BCD adder is designed that selects either a normal result or an excess-6 result. Conventional BCD adders are constructed using two ripple-carry binary adders and additional correction logic. The performance of BCD adders can be enhanced by optimizing their internal binary adders. This paper proposes an optimized 4-bit Excess-6 select BCD adder (E6BCD) using a new Excess-6 Block (E6B) in the second stage. The second 4-bit binary adder is replaced with a new E6B, which reduces circuit complexity, transistor count, power dissipation, and delay. A novel E6BCD topology uses a 10:5 multiplexer that allows the selection of either a normal result (less than or equal to 9) or an excess-6 result based on the correction logic output fed to the selection line. All the proposed and existing designs were simulated and synthesized at 90 nm technology using cadence tools, that is, Innovus and Genus. By eliminating the binary adder and unnecessary addition, even if the result is less than or equal to 9, the proposed E6BCD outperforms the existing designs in terms of speed and power by 25% and 15%, respectively.