Frequency-Dependent TDDB Modeling Based on Trapping Dynamics

In this article, we present a new modeling approach to analyze the effect of pulsed stress frequency on the time to breakdown of high-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$</tex-math> </inline-formula> metal gates in CMOS transistor devices. First, we compare DC time-dependent dielectric breakdown (TDDB) and AC TDDB results obtained from samples fabricated using 28 nm FDSOI technology from STMicroelectronics. Then, we review the possible hypotheses that could explain the improvement in gate dielectric time to breakdown under pulsed stress. We provide details of a trapping-based TDDB model and compare the modeled effects of stress frequency on key TDDB parameters, such as median time to breakdown and voltage acceleration exponent, with experimental results. Finally, we apply the model findings to digital and RF circuit test cases to investigate the impact of frequency effects on product reliability margins.