Low-Area and Low-Power VLSI Design for Remote Patient Health Monitoring Systems

This paper presents a low-area and low-power VLSI architecture for remote patient health monitoring systems, which demand highly integrated, energy-efficient hardware capable of continuous physiological sensing, local processing, secure communication, and long operational lifetime under constrained power budgets. The proposed design minimizes silicon area and dynamic/static power while preserving the accuracy and responsiveness required for medical-grade monitoring. Key features include a mixed-signal sensor front-end optimized for minimal area, a low-power successive-approximation ADC with event-driven sampling, lightweight feature-extraction hardware to reduce data motion, a compact neural accelerator for on-edge inference using quantized models, and an integrated power management and security engine. Design choices emphasize standard-cell and custom mixed-signal co-design, multi-threshold libraries, clock and power gating, sub/near-threshold operation for selected blocks, and compressed on-chip memory to reduce footprint. The methodology is evaluated through RTL synthesis, place-and-route, and post-layout power and area analysis on representative physiological workloads such as ECG, PPG, and accelerometer signals.