Maximum FPGA: A 32K-Point 32-Parallel Floating Point FFT

FPGAs offer a powerful and flexible platform to build complex systems on. But the potential - both in density and clock frequency - is often missed. In this work we present a massively parallel FFT, which can process a 32 K point FFT with 32-parallel IEEE-754 single-precision floatingpoint streams of complex data. Each core uses 1281 DSP Blocks, and can be packed into a near 100 % DSP Block density in an Altera Agilex-7 FPGA. Six such cores have been instantiated in a system, using 90 % of the device capability. In all cases our designs close timing at nearly 770 MHz, which is the restricted frequency of the DSP Block in floatingpoint mode. The contributions of this work are manifold. We demonstrate approaches that can be used to fill even larger FPGAs to high density with high performance. We also introduce optimizations for the FFT that can be used by all types of (including non-FFT) applications, from simple implementations to the very large parallel examples we use to demonstrate our research.