Suppression of hysteresis in ultrathin tellurium transistors

Tellurium (Te) is a promising p-type semiconductor but suffers from pronounced electrical hysteresis that limits device stability. The origin of hysteresis in Te field-effect transistors is investigated, and effective suppression strategies are demonstrated. In exposed devices, large hysteresis and abrupt current switching are observed, governed by the direction and range of gate voltage sweeps rather than gate polarity, and are attributed to the dynamic reorientation of dipolar gas molecules adsorbed on the Te surface. Dielectric encapsulation using Al2O3 significantly suppresses gas-induced hysteresis, resulting in improved mobility of ~80 cm2 V-1 s-1 and an ION/IOFF ratio exceeding 105 under ambient conditions. Nevertheless, residual hysteresis associated with charge trapping persists in single-gate devices. To further stabilize channel electrostatics, a dual-gate architecture employing Al2O3 top and bottom dielectrics is implemented, achieving hysteresis below 1 V across a wide range of sweep rates and exhibiting minimal degradation under prolonged bias stress. These results establish a comprehensive understanding of hysteresis in Te and enable reliable, BEOL-compatible p-type transistors for advanced integration.