Design of a Multi-Core Hybrid CMOS-Memristor Chip for Analog Programming

The emergence of memristive devices and their integration with CMOS technology promises a revolutionary leap in ultra-efficient in-memory analog computing, particularly for neuromorphic and AI applications. However, this potential is currently limited by the challenge of precisely programming intermediate, analog resistive values. Conventional iterative Program-and-Verify algorithms are time-consuming and accelerate device degradation due to numerous write/erase cycles. To overcome this, we propose a novel analog programming circuit that uses a ramp voltage generator and a current comparator to set the desired resistive value in a single iteration, minimizing programming time and device degradation. In this work, we have implemented a single-iteration programming circuit within a multi-core hybrid CMOS-memristor architecture with 9k memristors on a chip fabricated using GlobalFoundries 22 nm FDSOI technology, which will be used to characterize the proposed approach, demonstrating a viable path toward high-precision and robust large-scale analog computing systems.