Low Power and Low Complexity 0.3 V CMOS Voltage References Using Single $V_{T}$ MOSFETs

In this work, we present two low-power CMOS voltage references which exploit the effect of MOSFET's length on its threshold voltage. The result of utilizing this technique are low complexity, fully subthreshold designs, which can use single <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{T}$</tex> NMOS and PMOS transistors only. One of the designs provides an improvement of two orders of magnitude in line sensitivity thanks to a technique which does not require cascodes. The designs are simulated in a 180 nm technology and the layout of the highest performing design is presented. The best design generates an output of 72.6 mV at 25 °C, with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$102 \text{ppm} /{ }^{\circ} \mathrm{C}$</tex> temperature coefficient between <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-20^{\circ} \mathrm{C}$</tex> and 80 °C, a supply sensitivity of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.19 {\%} \mathrm{V}^{-1}$</tex>, while consuming 1.87 nW.