Theoretical Analysis and Digital Circuit Design for a New PD-Type Iterative Learning Controller

This paper investigates a new design method for PDtype iterative learning control (ILC). Specific design and adjustment approaches are proposed separately for the P-type control learning gain and the D-type control learning gain in order to accelerate the convergence rate of the learning error. In particular, the adjustment of the D-type control learning gain adopts an intelligent gain adjustment rule based on a fuzzy system. In addition to theoretical proof and analysis, a numerical example is conducted and verified through simulations using Matlab software. Furthermore, the control algorithm is implemented as a digital circuit using the Verilog hardware description language. After its correctness is verified on the Quartus II platform, the design is realized on an FPGA chip to demonstrate its feasibility.