Optimization of electrical properties of carbon nanotube field-effect transistors by gate oxide parameters and strain

Abstract Carbon nanotube field-effect transistors (CNTFETs) have demonstrated superior performance in integrated devices compared to conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), with optimizations achieved through precise control of chirality, nanotube count, and channel length scaling. However, while these parameters significantly influence device characteristics, the effects of gate oxide engineering and strain-induced field modifications remain incompletely understood, requiring further investigation to fully exploit the potential of CNTFETs. In this study, we systematically investigate these phenomena by combining current transport modeling with first-principles calculations. Our analysis reveals that gate oxide thinning enhances drain–source current by improving gate control, but necessitates high- $$\kappa$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mi>κ</mml:mi> </mml:math> dielectrics (≥ 25) to suppress direct tunneling leakage through Poisson’s equation solutions. At $$\kappa =25{\varepsilon }_{0}$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:mi>κ</mml:mi> <mml:mo>=</mml:mo> <mml:mn>25</mml:mn> <mml:msub> <mml:mi>ε</mml:mi> <mml:mn>0</mml:mn> </mml:msub> </mml:mrow> </mml:math> , we achieved optimized FET metrics: saturation current (12 $$\upmu\mathrm A$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:mi>μ</mml:mi> <mml:mi>A</mml:mi> </mml:mrow> </mml:math> ), transconductance (277 $$\upmu\mathrm S$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:mi>μ</mml:mi> <mml:mi>S</mml:mi> </mml:mrow> </mml:math> ), and gate–source capacitance (103.4 $$\text{aF}$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mtext>aF</mml:mtext> </mml:math> ), representing improvements over conventional SiO 2 -based designs. Furthermore, under uniaxial radial compressive strain ( $${\varepsilon }_{\text{yy}}$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:msub> <mml:mi>ε</mml:mi> <mml:mtext>yy</mml:mtext> </mml:msub> </mml:math> = 0.66), the saturation current increases by ~10 times compared to the unstrained case due to decreasing bandgap, while the threshold voltage and the subthreshold swing increase by ~2 times as well, lowering transistor switching efficiency and increasing power consumption. Therefore, strain engineering can provide a valid approach for performance-targeted design: high-frequency power amplifiers with large strains and low-power logic gates with small strains.