Implementation-Aware UPF Methodology for Managing Power Domain Crossings in Multi-Voltage SoCs

Aggressive power targets in mobile, IoT, and automotive SoCs have driven extensive use of multi-voltage and power-gated domains, making power domain crossings a major source of overhead and bugs. Power in- tent is usually specified in UPF at a high level, and generic rules for isolation, level shifting, and retention are pushed into implementation, which can lead to an excessive number of special cells, timing loss, routing congestion, and difficult lowpower sign-off. This work proposes an implementation-aware power domain crossing (PDC) methodology tightly integrated with a Cadence Innovus-based flow. First, a clustering-based partitioning strategy groups strongly communicating blocks into common domains to minimise crossings and the number of special cells. Second, an optimised UPF boundary strategy tailors isolation, level-shifting, and retention policies to specific domain relationships and power modes, avoiding redundant instrumentation while preserving correctness. Third, a complete RTL UPF physical design flow is presented, with quantitative evaluation of area overhead, timing impact, power savings, and low-power verification violations against a conventional UPF baseline. Results for representative multidomain SoC subsystems show that the proposed approach significantly reduces domain crossings and special cells while maintaining sign-off quality, turning PDC from a lateimplementation side effect into a controllable design parameter.