Energy-Efficient Sequential Circuit Design Using Optimized Clock-Gated Johnson Counter for Low Power VLSI Applications

In modern VLSI design, minimizing power consumption is a critical requirement for battery-operated and portable electronic systems. Conventional sequential circuits, such as Johnson counters, suffer from high dynamic power dissipation due to continuous and redundant clock toggling, even during idle or low-activity states. This project presents an energy-efficient sequential circuit design using an optimized clock-gated Johnson counter to overcome these limitations. The proposed design employs clock-gating techniques to selectively disable the clock signal during inactive periods, thereby reducing unnecessary switching activity without affecting functional performance. The architecture is implemented using Verilog HDL and verified through simulation, synthesis, and power analysis. Functional correctness and power efficiency are further validated through hardware implementation on an ALTERA FPGA CYCLONE – II. Comparative analysis with conventional Johnson counter designs demonstrates significant power savings, making the proposed approach well suited for low-power VLSI applications. Keywords: Clock gated, Johnson Counter, VLSI design, Power dissipation, Vivado, Quartus, VLSI application etc.