FPGA-Specific Accurate and Approximate Compressor-based Multipliers Using Column Restructuring and Post-Synthesis Approximation

This repository contains the implementation and evaluation framework for FPGA-based accurate and approximate multiplier designs developed using VHDL and implemented on the xc7a15tcpg236-2 device using Vivado. The repository provides all necessary files to reproduce the experimental results, including design sources, testbenches, input datasets, and analysis scripts. Both accurate and approximate multiplier architectures (8-bit and 16-bit) are included, along with pipelined implementations for performance evaluation. Error analysis for the 8-bit multiplier is performed using exhaustive simulation with provided input and output datasets, while the 16-bit multiplier is evaluated using a Monte Carlo-based approach implemented in MATLAB. Timing and power analyses are carried out using standard Vivado implementation and switching activity (.saif) based estimation. All results are generated using the codes and scripts included in this repository, ensuring full reproducibility. The repository also includes detailed instructions for project setup, simulation, and analysis. In addition, figures aiding in the design and implementation of the proposed architectures are also provided within the repository for better clarity and understanding. The repository also contains the Set12 dataset that includes the "Cameraman.tiff" image used in the manuscript. The dataset is readily available and is free to use under Creative-Common 0 License agreement.