Topology Optimization of Backside Films to Mitigate Semiconductor Wafer Warpage

Abstract Wafer warpage is a critical challenge in semiconductor fabrication that adversely affects manufacturing yield and device reliability. This challenge is intensifying due to increased device integration and significant thermal mismatches among deposited films. This study presents an approach that integrates Finite Element Method (FEM) simulations with Topology Optimization (TO) to mitigate wafer warpage by optimizing the back-side film. This method generates counteracting stresses designed to offset the original warpage. First, FEM simulations accurately captured the thermally induced warpage of a bi-layer reference wafer to establish a baseline profile. Then, TO identified the optimal back-side film configuration to minimize this warpage. Compared to conventional full-film attachment, the proposed method significantly reduces warpage while using less back-side film material. The approach was validated across “smile”, “cry”, and “saddle”-type warpage scenarios, demonstrating that simulation-driven TO is an effective strategy for enhancing integrated circuit reliability and manufacturing productivity.