Low-power logic circuit realization using dual-gate tunnel FETs with Ge–Si heterostructures

This paper presents the design and TCAD-based simulation of fundamental logic gates OR, NAND, AND, and NOR using Dual-gate tunnel FET(DG-TFET). The OR and NAND gates are implemented using p-type and n-type DG-TFET, while AND and NOR gates are engineered through gate-source/drain overlap and optimizing <i>t</i>_si . The electrical performance of each logic gate is evaluated based on <i>I_D</i>–<i>V_G </i>characteristics, ON current (<i>I</i>_ON), OFF current (<i>I</i>_OFF), and the switching ratio (<i>I</i>_ON/<i>I</i>_OFF). Due to the inherently low <i>I</i>_ON in siliconTFET, germanium (Ge) is introduced at the source to enhance BTBT. Simulation results demonstrate that Ge integration significantly increases <i>I</i>_ON by nearly two and three decades across NAND and NOR gate types respectively. For instance, in the case of the NAND gate, <i>I</i>_ON enhanced from 5.04 × 10⁻⁶ A/<i>µ</i>m to 4.56 × 10⁻⁴ A/<i>µ</i>m with Ge. These findings suggest that with proper material selection and structural optimization, DG-TFETs hold strong potential as energy-efficient options for next-generation low-power logic applications.