Measurement Techniques for Power Analysis in Side-Channel Attacks on Integrated Circuits

This article examines the evaluation of hardware security against side-channel attacks (SCA) during the prototyping phase of digital integrated circuits. A study was conducted on the correlation between measurement equipment parameters (bandwidth and sampling rate) and the effectiveness of correlation power analysis (CPA) for an AES-128 encryption algorithm implementation on an FPGA. A specialized measurement methodology is proposed, including calibration, integration of protection mechanisms, leakage differentiation, and effectiveness assessment. Experimental verification focuses on the calibration phase using a specialized measurement setup with variable bandwidth (20–500 MHz) and sampling rate (50–5000 MS/s). The results show that limiting the bandwidth significantly improves the signal-tonoise ratio (SNR) and reduces the number of traces required for key recovery. Furthermore, the study reveals the influence of input data entropy on leakage metrics. These results enable optimization of leakage detection setups, reducing computational and hardware costs while maintaining high assessment reliability.