Optimized Arithmetic Architecture in Cryptographic Processor for IoT Embedded System

The arithmetic architecture of a cryptographic processor with a low-power and high-throughput model with Internet-of-things (IoT) nodes using minimal resources. Resourceconstrained Internet of Things (IoT) devices demand cryptographic solutions that offer strong security with minimal power and hardware overhead. In this work, an optimized arithmetic architecture for a cryptographic processor is presented, targeting low-power IoT embedded systems. The proposed design focuses on improving modular arithmetic operations by replacing conventional adder–multiplexer structures with a LUT-based arithmetic unit optimized for FPGA implementation. This architecture reduces critical path delay, power consumption, and logic utilization while supporting essential cryptographic operations such as modular addition and subtraction. The design is implemented and verified on a Xilinx FPGA using Vivado, where performance is evaluated in terms of power, delay, and power–delay product (PDP). Experimental results demonstrate a significant reduction in power consumption (up to 50%) and improved PDP compared to the existing architecture, validating the suitability of the proposed design for energy-efficient and secure IoT applications.