ATPG-Compliant Digital Modeling of MRAM for Cell-Aware Testing

As memory complexity increases, traditional fault models are falling short in ensuring test quality. Cell-Aware (CA) testing, using post-layout transistor-level analysis, has proven effective for static random access memory (SRAM). The methodology uses detailed CA models which are further processed by Automatic Test Pattern Generators (ATPG) to create targeted test patterns that ensure high fault coverage. Despite its success in digital circuits, the application of ATPG-based CA testing to emerging non-volatile memory technologies such as Magnetic Random Access Memory (MRAM) remains largely unexplored. In this work, we propose a methodology dedicated to MRAM testing by developing a Verilog model derived from an analog SPICE netlist. This digital model accurately captures the architectural and behavioral traits of the underlying MRAM cell, ensuring compatibility with standard digital test tools such as Automatic Test Pattern Generators (ATPG). The proposed framework enables the generation of ATPG-based test patterns and supports fault simulation, paving the way for realistic, robust and accurate test strategies for MRAM devices.