Fractional Fourier Transform-Oriented Hardware Design for Normalized-Domain Chirp Synthesis

The fractional Fourier transform (FrFT) extends the conventional Fourier transform (FT) by providing a continuous spectrum of transformations between the time and frequency domains. Its distinctive properties make it particularly suitable for the analysis of non-stationary signals, which is a critical requirement in detection and classification applications. Despite its potential, few studies have investigated hardware implementations of the FrFT, and those that exist often overlook the implementation challenges and design details of the chirp functions at its core. This work introduces a modular hardware architecture for the generation of complex, domain-independent chirp signals that form the basis of the digital computation of the FrFT. The realized design leverages a numerically controlled oscillator (NCO)-driven approach within a model-based design framework and is implemented on the XC7Z020-CLG484-1 system-on-a-chip (SoC). Experimental results demonstrate that the architecture faithfully reproduces the outputs of established software implementations and operates at a high clock frequency for this device class. Furthermore, the design supports flexibility in the transform's parameters, making it well-suited for reconfigurable signal processing systems.