A 1.3-GOPS parallel DSP for high-performance image-processing applications

A programmable digital signal processor (DSP) for real-time image processing is presented that combines the concepts of single-instruction multiple-data (SIMD) and very long instruction word with a high utilization of parallel resources on instruction and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image-processing requirements and follows two basic rules: shared data have to be accessed regularly in the shape of a matrix and are stored in the matrix memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The matrix memory allows parallel, conflict-free access from all datapaths in a single clock cycle. The DSP achieves 1.3-GOPS performance at 66 MHz. A first prototype in 0.5-/spl mu/m CMOS technology has been fabricated.