On-Chip Interconnection Networks of the TRIPS Chip

200783 citationsJournal Article

Authors

Paul V. Gratz · The University of Texas at Austin

Changkyu Kim · Intel (United States)

Karthikeyan Sankaralingam · University of Wisconsin–Madison

Heather Hanson · IBM (United States)

Premkishore Shivakumar · The University of Texas at Austin

Stephen W. Keckler · The University of Texas at Austin

Doug Burger

Abstract

The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.

Topics & Keywords

Interconnection Networks and Systems Low-power high-performance VLSI design VLSI and FPGA Design Techniques

Publication Details

Published in: IEEE Micro

Volume 27, Issue 5, pp. 41-50

DOI: 10.1109/mm.2007.90

Field-Weighted Citation Impact: 8.98

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On-Chip Interconnection Networks of the TRIPS Chip

Authors

Abstract

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Publication Details