EMC studies for the vertex detector of the Belle II experiment

The upgrade of the Belle II experiment plans to use a vertex detector based on two different technologies, DEPFET pixel (PXD) technology and double side silicon microstrip (SVD) technology. The vertex electronics are characterized by the topology of SVD bias that forces to design a sophisticated grounding because of the floating power scheme. The complex topology of the PXD power cable bundle may introduce some noise inside the vertex area. This paper presents a general overview of the EMC issues present in the vertex system, based on EMC tests on an SVD prototype and a study of noise propagation in the PXD cable bundle based on Multi-conductor transmission line theory.