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Thermal interface materials (TIMs) play a critical and unavoidable role in heterogeneously integrated semiconductor packages. They are of increasing importance as chips emit heat fluxes exceeding $\lt sup\gt1\lt/sup\gt|00 \mathrm{~W} / \mathrm{cm}^{2}$. Metal TIMs and, particularly, solder thermal interface materials (solder-TIM or STIMs) are being utilized due to their unique properties, including high bulk thermal conductivity and good ductility, to improve the heat dissipation of the package. These solder TIMs use indiumbased alloy preforms of various thicknesses that are soldered to the metallized silicon dies and copper lids. While packages with STIM demonstrate very low thermal resistance, their long-term thermal performance requires further investigation. Accelerated thermal cycling is one of the industry standard reliability tests that is used to evaluate potential degradation in electronic packages over their expected lifetime. This work investigates the stability of these solder TIMs during thermal cycling for test coupons made with an optimized vacuum reflow process for each of the solder alloys. These coupons have a cross-section of $\mathbf{4 0 ~ m m \times 4 0 ~ m m}$ to represent chips with large dies. The defect rate and warpage changes for the different solder alloys in the TIM layer are studied during temperature cycling for voids, delaminations, etc. using scanning acoustic microscopy and X-ray imaging alongside warpage measurements using a shadow-moiré technique. Temperature cycling generally causes an enlargement of defects and cracking in the solder layer, especially for solder TIM layers used in packages with larger dies. This is primarily due to the strain caused by the different coefficients of thermal expansion of the copper lid and the silicon die. The large die size can lead to defects by modes including void enlargement, interfacial delamination, solder crack formation, or solder failures, all of which will affect the solder TIM thermal performance. The solder defect fraction is reported as a function of thermal cycles. The solder TIM layer in the test coupons had an initial areal defect coverage of 0.5-3% which would grow by more than $\mathbf{4 0 \%}$ over the 1000 temperature cycles.